5G NR Frame Structure Visualized — Frame, Slot, Symbol, Mini-Slot Side-by-Side

Reading TS 38.211 §4.3 about frame structure is dense. Once you've seen the same content as a diagram, the spec text reads like a caption. This guide is a visual-first walkthrough.

The 10 ms Frame

The fundamental cycle. 1 frame = 10 ms = 10 subframes = 2 half-frames. Identical to LTE for backward compatibility.

┌──────────────────────── 10 ms FRAME ────────────────────────┐
│ SF0 │ SF1 │ SF2 │ SF3 │ SF4 │ SF5 │ SF6 │ SF7 │ SF8 │ SF9 │
└──────────── HALF-FRAME 0 ────┴──────── HALF-FRAME 1 ──────┘
              5 ms                       5 ms

The 1 ms Subframe — Invariant

1 subframe = 1 ms always, regardless of numerology. This is the timing anchor for all per-ms timers (RA-RNTI windows, k1 PUCCH offset for some configs).

Slots Per Subframe Depend on Numerology

μ=0 (15 kHz)  ┌────────────────── 1 ms ──────────────────┐
              │            slot 0 (1 ms · 14 sym)           │
              └────────────────────────────────────────────┘

μ=1 (30 kHz)  ┌──────── 0.5 ms ────────┐──── 0.5 ms ────┐
              │  slot 0 (14 sym)        │ slot 1          │
              └────────────────────────┘─────────────────┘

μ=2 (60 kHz)  ┌─250μs─┐─250μs─┐─250μs─┐─250μs─┐
              │  s0   │  s1   │  s2   │  s3   │
              └───────┴───────┴───────┴───────┘

μ=3 (120 kHz) ┌─125─┬─125─┬─125─┬─125─┬─125─┬─125─┬─125─┬─125─┐
              │ s0  │ s1  │ s2  │ s3  │ s4  │ s5  │ s6  │ s7  │
              └─────┴─────┴─────┴─────┴─────┴─────┴─────┴─────┘

14 Symbols Per Slot — Not Equal

Within a slot of 14 OFDM symbols (Normal CP), symbols 0 and 7·2^μ have a slightly longer cyclic prefix to absorb the 1ms − 14·N_u remainder.

Slot at μ=0:
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |
[L][N][N][N][N][N][N][L][N][N][N][N][N][N]   (L = long CP, N = normal)

Mini-Slots — URLLC Magic

Instead of waiting for the next slot boundary, URLLC traffic can grab 2/4/7 symbols anywhere in a slot.

Normal slot scheduling (PDSCH Type A):
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |
[ control ][          PDSCH (full slot)               ]

Mini-slot (PDSCH Type B):
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |10 |11 |12 |13 |
[ control ][        ][URLLC][        ]    (URLLC at sym 5-6)

TDD Slot Patterns

Each symbol can be Downlink (D), Uplink (U), or Flexible (F).

eMBB (Format 28 — DL-heavy):
[D][D][D][D][D][D][D][D][D][D][D][D][F][U]
12 DL · 1 F · 1 U

URLLC (UL-heavy):
[D][D][D][D][F][U][U][U][U][U][U][U][U][U]
4 DL · 1 F · 9 U

Industrial / sensors (balanced):
[D][D][D][D][D][D][D][F][U][U][U][U][U][U]
7 DL · 1 F · 6 U

The Five Layers — One Diagram

Frame          ████████████████████████████████████  (10 ms · reference)
Half-Frame     ██████████████████                    (5 ms · SSB & paging)
Subframe       ████                                  (1 ms · timing anchor)
Slot (μ=1)     ██                                    (500 μs · scheduling unit)
Symbol         ▌                                     (33 μs · atomic OFDM unit)

Once you can sketch this from memory, you can navigate any TS 38.211 §4.3 reference and any drive-test log entry. The full course (Lessons 1-3 through 1-6) walks through each layer in detail with cinematic SVG animations. $29 lifetime.